ROSS Technical Support

Technical Publications

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Rescued from oblivion by the Wayback Machine, and mirrored here for my own convience. Mirror created on 27-Jan-2003.

ROSS Company Backgrounder (69k)

hyperSPARC White Paper (476k)

SPARCplug White Paper (257k)

hyperSPARC and Multiprocessing Performance (92k)

MDP Improves Microprocessor Design (96k)

Anatomy of a hyperSPARC Module (164k)

Multiprocessing Symmetry (86k)

32 bit -vs- 64 bit Applications (93k)

hyperSPARC Data Sheet - 125 MHz/256K cache single CPU

hyperSPARC Data Sheet - 142 MHz/1M cache dual-wide CPU

hyperSPARC Data Sheet - 150 MHz/512K cache dual CPU

hyperSPARC Data Sheet - 128 DRAM Memory Module

hyperSPARC Data Sheet - Colorado II 90, 100, 125 MHz/256K cache single CPU

hyperSPARC Data Sheet - Colorado III 125-166 MHz/512K cache single CPU

hyperSPARC Data Sheet - Colorado IV 180, 200 MHz/512K cache single CPU

hyperSPARC Data Sheet - Rocky II 90, 100, 125 MHz/256K cache dual CPU

hyperSPARC Data Sheet - Colorado II 90, 100, 125 MHz/256K cache dual CPU

hyperSPARC Data Sheet - Colorado III 125, 150 MHz/512K, 1M cache dual CPU

hyperSPARC Data Sheet - Colorado III 142, 150 MHz/512K, 1M cache dual-wide, dual CPU

hyperSPARC Data Sheet - Colorado III 142 MHz/1M cache dual CPU power module

Copyright 1996 - ROSS Technology, Inc.